1. Field of the Disclosure
Generally, the present disclosure relates to the field of semiconductor devices formed on the basis of integration schemes that provide increased overall packing density.
2. Description of the Related Art
Significant progress has been made over the past decades in the field of semiconductor devices by continuously reducing critical dimensions of the individual circuit elements, such as field effect transistors and the like. Basically, reducing the overall lateral dimensions of transistors and other circuit elements has resulted in an enormous packing density in complex semiconductor devices, wherein several hundred millions of individual transistor elements may be provided in a single semiconductor chip representing a complex central processing unit. Implementing reduced lateral dimensions increases the packing density, in particular, in critical device regions, such as static and dynamic RAM (random access memory) regions, wherein a large number of transistor elements, possibly in combination with a storage capacitor, may have to be provided within restricted areas of the semiconductor device so as to provide high information density. This reduction in size has been accompanied by significant advantages with respect to transistor performance. As a typical example, the increased switching speed of transistors in critical signal paths may allow operation of control circuitry at significantly increased clock frequencies and, thus, increased operating speed.
Despite the many advantages associated with the continuous reduction of critical dimensions of semiconductor devices, however, a plurality of side effects accompanying these developments may have to be taken into account so as to not unduly offset the effects obtained by increasing operating speed and packing density. For example, upon continuously reducing the gate length of transistor elements, controllability of the corresponding channel of transistor elements may require significant efforts so as to provide the required functional behavior, even for highly sophisticated short channel transistors. In other aspects, overall parasitic capacitance in sophisticated transistor elements may contribute to a less than expected performance gain, as, for instance, a non-fully depleted channel region, in combination with the presence of a bulk region, may result in reduced operating speed of respective transistor elements, even if formed on the basis of extremely reduced vertical dimensions of 30 nm and even less. As a consequence, the increasing difficulties in providing sufficient channel controllability and non-negligible parasitic capacitance of the transistor body have driven respective developments in providing superior transistor configurations. For example, in some sophisticated approaches, “three-dimensional” transistor architectures may be used on the basis of respective semiconductor fins, which may have two or more surface areas that may be controlled by a surrounding gate electrode structure, thereby not only enhancing channel controllability, but also contributing to increased current drive capability. In other approaches, significant efforts have been made to provide sophisticated gate electrode structures on the basis of sophisticated material systems in order to achieve superior channel controllability, while still preserving the well-established planar transistor architecture.
Irrespective of the transistor architecture used, a so-called “SOI” (silicon- or semiconductor-on-insulator) architecture may be applied in an attempt to further reduce the parasitic capacitance of the transistor body or transistor channel, while also enhancing isolation of the transistor body from the surrounding device areas. In an SOI architecture, a buried insulating layer, for instance, comprising silicon dioxide, silicon nitride and the like, is typically formed below a respective semiconductor layer, such as a crystalline silicon layer, a crystalline silicon/germanium layer, a crystalline silicon/carbon layer and the like, in and above which a respective transistor element may be formed. Consequently, in addition to lateral isolation structures, such as shallow trench isolations, the buried insulating layer may result in a substantially complete insulation of respective transistor regions, thereby providing superior conditions during the operation of the transistor element.
As discussed above, the planar transistor architecture is generally based on well-established technical concepts that have been proven highly efficient over the past decades. Therefore, appropriate strategies have been developed which may be further adapted to strategies requiring even further reduced critical dimensions. On the other hand, the implementation of three-dimensional transistor architectures is accompanied by a plurality of sophisticated processes, which may significantly contribute to the overall manufacturing costs.
For these reasons, the concept of a planar transistor architecture has been further developed in view of overcoming many of the technical problems involved in the further reduction of critical dimensions of planar SOI transistor elements. As discussed above, highly complex gate electrode structures may be typically used for obtaining the desired channel controllability, which, however, may still require additional measures so as to allow a further reduction of respective channel lengths. One mechanism in this respect may provide superior controllability of basic transistor parameters, such as threshold voltage and the like, in combination with superior channel controllability, wherein an additional control voltage may be applied to a conductive region positioned below the buried insulating layer and, thus, enabling influence on charge carriers in the semiconductor layer across the buried insulating layer. A corresponding additional control voltage may also be referred to as “back bias” and the corresponding concept will be referred to herein as “back bias mechanism.” That is, taking advantage of the SOI architecture, the buried insulating layer may be considered as a dielectric barrier, which, nevertheless, may still provide the possibility of establishing certain electrostatic influence on charge carriers in the channel region by providing an appropriately doped semiconductor region below the buried insulating layer, which may be additionally connected to an appropriate reference voltage source so as to provide an additional control voltage “on demand.” Consequently, superior static and dynamic behavior of field effect transistors based on an SOI architecture may be achieved by using the back bias mechanism.
Moreover, in a further attempt to enhance overall transistor performance, a fully depleted transistor configuration may be established. This is typically accomplished by reducing a respective thickness of at least the channel region of transistor elements, so that, in a certain state of the transistor element, the respective channel region may be substantially fully depleted with respect to the majority charge carrier.
Although the concept of a fully depleted SOI transistor provides significant performance gain and, thus, allows the configuration of highly complex semiconductor devices, including a large number of transistor elements, it turns out, however, that further reduction of critical dimensions in the area of 30 nm and less may result in significant technical problems that may have to be overcome when striving to further enhance overall packing density of highly complex semiconductor devices. While, on the other hand, a corresponding increase of packing density on the basis of three-dimensional transistor architectures may be associated with significant technical challenges, as well as with significant manufacturing costs, significant efforts have been made in order to mitigate at least some of the technical problems associated with further device scaling, in particular in planar technologies.
For example, U.S. Patent Publication No. 2013/0089978 discloses an integrated circuit formed on the basis of transistor elements based on fully depleted SOI architecture, in which a common well region, i.e., a doped region formed below the buried insulating layer, may be used for a P-type transistor and an N-type transistor, wherein the commonly used well region may be used for biasing inversely doped back bias regions of the respective complementary transistors.
In other approaches as, for instance, disclosed in U.S. Pat. No. 7,821,066, the buried insulating layer may be provided as a multi-layered component, thereby specifically designing the characteristics of the buried insulating layer. EP 0843344 B1 discloses a process for transferring a semiconductor layer by using well-established SOI techniques. Similarly, U.S. Pat. No. 7,960,248 discloses a method for transferring a thin layer.
Although the technical approaches disclosed in these prior art documents may aim at enhancing transistor performance based on well-established fully depleted SOI architectures and/or increasing overall packing density, for instance, by contemplating the transfer of semiconductor layers for providing the possibility of forming stacked device configurations, it turns out, however, that these approaches are less than desirable in view of appropriately enhancing packing density while preserving superior transistor controllability, for instance, by using a back bias mechanism.
In view of the situation described above, the present disclosure relates, therefore, to semiconductor devices and manufacturing techniques in which the packing density may be increased, while preserving well-established control mechanisms, such as a back bias mechanism, while avoiding or at least reducing the effects of one or more of the problems identified above.